WHY
Over the last decade, scaling of DRAM circuits for microprocessors, graphic subsystems, printers, etc. has posed one of the most difficult challenges for continued scaling of silicon ICs. In the single-transistor (1-T), single-capacitor (1-C) configuration of DRAM cells, the logic level is indicated by the presence or absence of charge (Q) stored in a capacitor node accessed by a pass transistor. Since, Q=CV, larger capacitance (C) and higher operating voltage (V) result in a high-performance cell with long retention time and robust noise immunity. However, since technology scaling over the years has reduced both capacitor area A and supply voltage V simultaneously, DRAM designers have pioneered the integration of high-k gate dielectric (Ta2O3, Al2O3, etc), invented many novel 3D capacitor structures (e.g., trench, fin, stack, etc.), and explored many innovative circuit architectures (from random access to page mode to hyperpage to burst extended data-out, etc.) to offset the detrimental effects of scaling and keep DRAM as a viable, high performance and low-cost memory technology for silicon IC. However, even this comprehensive "material, geometry, and architecture" based approach to DRAM scaling may no longer be viable beyond the 65 nm node, because the higher-k gate dielectrics like BST does not integrate well with CMOS and there is a limit of the aspect ratio of anisotropic etch that can be supported by conventional lithography for deep trench-capacitors. And any architectural solutions must grapple with limits imposed by rewrite-on-read and sub-1sec refresh time requirements of 1T-1C DRAM cells. Indeed, the scaling requirements (footprint 0.025 mm2 by 2016!) are so daunting that, according to IRPS roadmap, there is no known strategy to reach those scaling goals for DRAM.
Given these scaling roadblocks, DRAM scaling could continue only if the cell design did not involve scaling of capacitors, or better yet, if it did not require the external capacitor at all. Inspired by a similar concept for SOI structures, we propose a single-transistor, capacitor-less (IT-0C) DRAM cell based on silicon nanowire (Si-NW) that is fundamentally more scalable 1T1C cells and encapsulates, within a single transistor, the functions of both the pass-transistor and the external capacitor of the conventional DRAM cell.
WHO ARE INVOLVED
Nauman Z. Butt, Graduate Student, Purdue
H. Kufluoglu, Graduate Student, Purdue
G. Klimeck, Professor, ECE Purdue
BACKGROUND PAPERS
[1] IRPS Roadmap, http://public.itrs.net/Files/2001ITRS/PIDS.pdf
[2] Brent Keeth and R. Jacob Baker, "DRAM Circuit Design," IEEE Press Series on Microelectronic Systems, New York, 2001, S. K. Tweksbury and J. E. Brewer (Eds.).
[3] B. Prince, "High Performance Memories: New Architecture for DRAM and SRAM Evolution and Function," John Wiley & Sons, Ld. New York, 1999.
[4] J.-M. Sallese, S. Okhonn, P. Fazan, and M. Nagoga, "DRAM Concept on SOI," Proc. of MIXDES, 2002.
