Research: Microelectronic Reliability

Theory of Negative Bias Temperature Instability
Reliability-Aware Circuit Design
Determination of Soft-breakdown Location in 2D for Gate Oxide Reliability
Off-State Reliability in SOC MOSFETs

Our Publications on Reliabillity Physics

Theory of Negative Bias Temperature Instability

WHY

Negative bias temperature instability (NBTI) is one of the most serious reliability concerns for both analog and digital circuits. This involves hole-assisted breaking of Si-H bonds at the Si/SiO2 interface. These broken bonds trap charges which in turn reduce drive current and increase parasitic capacitance. Excessive NBTI degradation may therefore lead to timing faults and functional failure. We are developing a comprehensive theoretical framework for NBTI experiments so that one can make accurate predictions of NBTI degradation as a function frequency, voltage, and temperature. We expect that such predictive models will eventually allow NBTI-tolerant circuit design.

WHO ARE INVOLVED

Haldun Kuflouglu, Graduate Student Purdue
Souvik Mahapatra, Professor, IIT-Bombay
Dr. T. Nigam, MTS, Agere Systems

BACKGROUND PAPERS

[1] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, "Characteristics of the surface-state charge (Qss) of thermally oxidized silicon", J. Electrochem. Soc., 114, p.266, 1967.

[2] K. O. Jeppson, C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MOS devices", J. Appl. Phys., vol.48, pp.2004-2014, 1977.

[3] T. Yamamoto, K. Uwasawa, and T. Mogami, "Bias temperature instability in scaled p+ polysilicon gate p-MOSFETs", IEEE Trans. Electron Devices, vol.46, no.5, pp.921-926, 1999.

[4] M. Makabe, T. Kubota, and T. Kitano, "Bias temperature degradation of p-MOSFET: mechanism and suppression", in proc., Int. Rel. Phys. Symp., pp.205-209, 2000.

[5] S. Mahapatra, P. Kumar and M. Alam, "A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs", in proc., Int. Electron Device Meet., pp. 2003.

[6] M. Alam, "A critical examination of the mechanics of dynamic NBTI for p-MOSFETs", in proc., Int. Electron Device Meet., 2003.

[7] A. T. Krishnan et. al., "NBTI impact on Transistor and Circuit: Models, mechanisms and scaling effects", in proc., Int. Electron Device Meet., pp. 2003.

Reliability-Aware Circuit Design

WHY

Modern integrated circuits (IC) contain tens of millions of transistors. Traditional design of these integrated circuits has relied on the fact that these transistors have almost identical characteristics when they are initially made, and that the characteristics change little during their subsequent usage. Therefore, IC designers have worried about other things like the size of the IC, its speed, battery life, ease of debugging for errors, etc. And this traditional design approach has worked fine for last 25 years. But now-a-days the transistors are becoming so tiny that it is getting impossible to ensure that they have same geometrical and physical characteristics. Equally important, the characteristics of the small transistors can change rapidly when the consumer uses the product. Therefore the question we asked - and that we hope to answer through this research - is how would one design an integrated circuit if one can no longer rely on the uniformity of the transistors, but must account for the fact that each transistor is slightly different and that its property changes with time. One can always assume the very worst case and design for the slowest transistor, but clearly that would be very wasteful. We are proposing that a much better approach would be to first accurately understand why and how the transistor parameter change (of fluctuate) and to account for this variation explicitly from the very beginning of the IC design process. The design technique is no longer deterministic as it once were, but it now involves statistical design methodologies like making the slower transistors a little wider (transistor sizing) to compensate for their lack of speed or making sure that the architecture distributes the usage burden among a number of transistors so no one transistor becomes so slow that the IC fails. We think the results of our research will be very important, because from now on till the end of Moore's curve, this non-traditional, statistical approach may be the only viable way of designing ICs. This new approach will allow us to make faster or less power-consuming ICs with a given set of transistors, because designers can now be more aggressive in their design. And this in turn may also allow us more time to find alternatives to CMOS and ease the eventual transition to post-CMOS devices and systems.

WHO ARE INVOLVED

Haldun Kufluoglu, Graduate Student Purdue
Kunh Yuk Park, Graduate Student Purdue (with Prof. K. Roy)
K. Roy, Professor, ECE Purdue
Dr. B. Paul, Post-doctoral Fellow, Purdue

BACKGROUND PAPERS

[1] X. Tang, V. De, and J. D. Meindl, "Intrinsic MOSFET Parameter Fluctuations due to Random Dopant Placement," IEEE Transactions on VLSI Systems, vol. 5, pp. 369--376, 1997.

[2] C. Visweswariah, "Death, Taxes and Failing Chips," in IEEE/ACM 40th Design Automation Conference , 2003, pp. 343-347.

[3] C. Hu, "Future CMOS Scaling and Reliability," Proc. of the IEEE, 81(5), pp. 682-689, 1993. Also see, P. Yang and J. H. Chern, "Design for Reliability: the Major Challenge for VLSI," Proc. of the IEEE, 81(5), 730-744, 1993.

[4] M. Alam, B. Weir, and P. Silverman, "A Future of Function or Failure," IEEE Circuits and Devices Magazine, pp. 42-48, 2002.

[5] M. Alam, "A critical examination of the mechanics of dynamic NBTI for p-MOSFETs", in proc., Int. Electron Device Meet., pp. 345-348, 2003. [6] M. Alam and R. K. Smith, "A Phenomenological Theory of Correlated Multiple Soft-Breakdown Events in Ultra-thin Gate Dielectrics," in proc., Int. Reliability Phys. Symp., pp. 406-411, 2003.

[7] J. P. Fishburn and A. E. Dunlop, "TILOS : A polynomial programming approach to transistor sizing," IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems, pp. 326--328, 1985.

[8] S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, "An exact solution of the transistor sizing problem for CMOS circuits using convex optimization," IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems , pp. 1612--1634, 1993.

[9] H. Tennakoon and C. Sechen, "Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step," in IEEE/ACM International Conference on Computer Aided Design, pp. 395-402, 2002.

[10] T-.L. Chou and K. Roy, "Estimation of Activity for Static and Domino CMOS Circuits Considering Signal Correlation and Simultaneous Switching," IEEE Trans. Computer-Aided Des. Of Integrated Circuits, 15(10), pp. 1257-1265, 1996.

Determination of Soft-breakdown Location in 2D for Gate Oxide Reliability

WHY

Previously we have developed a general theory of the statistics of multiple breakdown events in ultra-thin gate dielectrics. We studied the times to successive breakdown and the locations of the breakdown spots to conclude that the temporal and spatial correlations among breakdown spots are weak and therefore if a transistor can survive the first breakdown event, its lifetime is likely to increase exponentially. However, some have pointed out that our previous analysis of spatial correlation has been confined to one-dimension and that it does not preclude 2D spatial correlation. Our current research focuses on developing the measurement technique of localizing the position of the breakdown spot in 2D and to use the data thus obtained to establish the degree of spatial correlation among breakdown spots.

WHO ARE INVOLVED

D. Monroe, Columbia University
B. Weir, MTS Agere Systems
P. Silverman, MTS Agere Systems

BACKGROUND PAPERS

[1] M. Alam and R. K. Smith, "A Phenomenological Theory of Correlated Multiple Soft-Breakdown Events in Ultra-thin Gate Dielectrics," in proc., Int. Reliability Phys. Symp., pp. 406-411, 2003.

[2] M. A. Alam, R. K. Smith, B. Weir, and P. Silverman, "Uncorrelated Breakdown in Silicon Integrated Circuits", in Nature, 6914, p. 378, 2002.

[3] M. A. Alam, R. K. Smith, B. Weir, and P. Silverman, "Statistically Independent Breakdown Events Redefine Oxide Reliability Specification", in Nature, in proc. of IEDM, 2002.

[4] F. Monsier, "Degradation Mechanisms During the Ultra-thin Oxide Failure" in 2003 INFOS Proc., pp. 1-6.

[5] B.P. Linder, and J.H. Stathis, "Statistics of Progressive Breakdown in Ultra-thin Oxides," in 2003 INFOS Proc., GS4, pp. 1-4.

[6] J. Sune, E. Wu, "Statistics of Successive Breakdown Event For Ultra-thin Gate Dielectrics", in 2002 IEDM Tech Digest, pp. 147-150.

Off-State Reliability in SOC MOSFETs

WHY

SOC designers integrate digital, analog, and I/O functions within the same chip to reduce cost and to optimize global performance. However, such global optimization do not allow optimization of individual groups of devices. Therefore, SOC designers often face unique optimization challenges that designers of digital-only or analog-only ICs do not encounter. The same is true for reliability engineers for SOC systems who must now grapple with new and unique reliability concerns that were not present in discrete designs. For example, to reduce processing costs and complexity, the I/O and the digital sections sometimes share CMOS devices with the same oxide thickness and S/D diffusions. Such dual use devices have new reliability concerns that cannot be classified as isolated manifestation of TDDB, HCI, and NBTI degradations and must be treated as a unique combination thereof. A particularly interesting case involves off-state degradation of dual-use, single oxide thickness MOSFETs with the source, substrate and gate grounded and the drain held high. By conventional wisdom, there is no TDDB risk because the effective stressed area, confined near the drain, is very small, and there are no HCI or NBTI reliability concerns because the device is turned off. As such, these failure modes are often not well understood and well characterized during process development. However, this is precisely the type of degradation that is known to cause failures for SOC systems and show up (unfortunately) as expensive field returns.

WHO ARE INVOLVED

S. Mahapatra, Professor, EE IIT-Bombay

BACKGROUND PAPERS

[1] E. Wu et. al, in proc., Int. Reliability Phys. Symp., 2004.

Our Publications on Reliabillity Physics