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Swaroop Ghosh

Ph.D. Student

 

Box #192, Electrical Engineering Bld

Northwestern Avenue, West Lafayette, IN-47906

Ph: 765-494-3372(O)

      765-426-8700(C)

Fax:765-494-3371

 

Research Interests:

  • Low-power, fault tolerant and adaptive system design for nanoscale technologies.

  • On-chip calibration, diagnosis and self-repair for improving reliability and yield.

  • Hybrid systems using emerging low-cost, low-power nano-electronic devices.

  • Non-silicon nano-electronics and application to bio-implantable devices.

Education:

  • PhD student, Electrical Engineering, Purdue University, 2004-present.
  • MS, Computer Engineering, University of Cincinnati, 2002-2004.
  • BE, Electrical Engineering, University of Roorkee (now IIT Roorkee, india), 2000.
     

Selected Publications (Complete list):

J1. Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, “CRISTA: A new paradigm for low-power and robust circuit synthesis under parameter variations using critical path isolation”, Trans. Computer Aided Design and Systems (TCAD), Nov 2007. 

J2. Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, and Kaushik Roy, “A novel delay fault testing methodology using low-overhead built-in delay sensor”, Trans. Computer Aided Design (TCAD), Dec 2006. 

J3. Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, “Low-power and testable circuit synthesis using Shannon decomposition based structural transformation”, ACM Trans. on Design Automation Electronic Systems (TODAES), 2007.

C1. Swaroop Ghosh and Kaushik Roy, “Exploring High-Speed Low-Power Hybrid Arithmetic Units at Scaled Supply and Adaptive Clock-Stretching”, Asia-Pacific Design Automation Conference (ASPDAC), 2008.

C2. Swaroop Ghosh, Patrick Ndai, and Kaushik Roy, “A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking”, Design, Automation and Test in Europe (DATE),2008.

C3. Jing Li, Swaroop Ghosh and Kaushik Roy, “A generic and reconfigurable test paradigm using low-cost integrated Polysilicon TFTs”, International Test Conference (ITC), 2007.

C4. Swaroop Ghosh, Pooja Batra, Keejong Kim and Kaushik Roy, “Process tolerant low-power adaptive pipeline design in scaled technologies”, Custom Integrated Circuits Conference (CICC), 2007.

C5. Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, “Low overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling”, Design, Automation and Test in Europe (DATE),2007.

C6. Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, “A new paradigm for low-power and robust circuit synthesis under parameter variations using critical path isolation”, International Conference on Computer-Aided Design (ICCAD), 2006.

C7. Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim and Kaushik Roy, “Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM”, Design Automation Conference (DAC), 2006.

C8. Arijit Raychowdhury, Swaroop Ghosh, and Kaushik Roy “A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning”, International On-Line Testing Symposium, 2005.

Patents:

P1. Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, “A new paradigm for low-power and robust circuit synthesis under parameter variations using critical path isolation”. Patent filed with Purdue University.

P2. Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim and Kaushik Roy, “Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM”, Patent filed with Purdue University.

P3. Jing Li, Swaroop Ghosh and Kaushik Roy, “Generic and reconfigurable test paradigm using low-cost integrated Polysilicon TFTs”, Patent filed with Purdue University.

Last updated: April 10, 2008