Hank (Henry G.) Dietz

WWW Home Page URL
http://dynamo.ecn.purdue.edu/~hankd/
EMail
hankd@ecn.purdue.edu
Phone
(765) 494 3357
FAX
(765) 494 3371
USMail
Hank Dietz, Associate Professor
School of Electrical and Computer Engineering
Purdue University
West Lafayette, IN 47907-1285

"Official" Bio

After two years as a double major in Electrical and Mechanical Engineering at Columbia University, Henry G. (Hank) Dietz transferred to the Polytechnic Institute of New York (now Polytechnic University), where he earned B.S., M.S., and Ph.D. degrees in Computer Science. He joined the faculty at Purdue University, West Lafayette, Indiana, in August 1986 as an Assistant Professor of Electrical Engineering. In 1992, Dietz was promoted to Associate Professor. He served as Chairman of the Computer Engineering Area from Spring 1993 through Fall 1994.

Dr. Dietz has authored or coauthored over 130 technical papers, primarily in the fields of optimizing, parallelizing, compilers and computer architecture (including tightly-coupled clusters). Key contributions include development of PCCTS, PAPERS, and a variety of compiler optimizations and architecture mechanisms based on the concepts of "compiler-oriented architecture." Agencies that have supported his research work include the National Science Foundation, the Office of Naval Research, IBM, Rome Laboratory, and the Army High-Performance Computing Research Center.

Dietz is currently the President of the Midwest Society for Programming Languages and Systems (MSPLS), and has participated in the organization of various conferences, including serving as Program Chairman for the 26th International Conference on Parallel Processing (ICPP97). He also has participated in the development of XFree86 and Linux. Within Purdue, he has developed and taught six courses covering compilers, operating systems, and parallel programming. With professors Coyle and Jamieson, Dietz co-founded the vertically-integrated project courses of Engineering Projects In Community Service (EPICS). He is also a faculty advisor for HKN Beta Chapter.

"Unofficial" Bio

Hank Dietz is an Associate Professor in Electrical and Computer Engineering at Purdue University. Depending on who you ask, his primary research area is either compilers or architecture; he seems to have trouble isolating one from the other. The stuff he does is always public domain, often very insightful, and occasionally useful.

Education

B.S.C.S.
Polytechnic Institute of New York
M.S.C.S.
Polytechnic Institute of New York
Ph.D.
Polytechnic University
Dissertation defended August 1986, A. David Klappholz advisor:
The Refined-Language Approach to Compiling for Parallel Supercomputers, 1987.

Faculty Positions Held

1983-1984
Adjunct Lecturer, Department of Electrical Engineering, Computer Science Division, Polytechnic Institute of New York.
1984-1986
Academic Associate, Department of Electrical Engineering, Computer Science Division, Polytechnic University, New York, New York.
1986
Adjunct Lecturer, Department of Electrical Engineering, Computer Science Division, Polytechnic University, New York, New York.
1985-1986
Adjunct Professor, Department of Computer Science, Stevens Institute of Technology, Hoboken, New Jersey.
1986-1992
Assistant Professor, School of Electrical Engineering, Purdue University.
1992-
Associate Professor, School of Electrical and Computer Engineering, Purdue University.
Fall 1997
On sabbatical at the Computer Science Department, School of Engineering and Applied Science, Washington University in St. Louis, St. Louis, Missouri.

Ph.D. Students Graduated

  1. Chi-Hung Chi (Lecturer, Chinese University of Hong Kong Dept. of CS), Compiler-Driven Cache Management Using a State Level Transition Model, 1989.
  2. Matthew O'Keefe (Assoc. Prof. of EE, U. of Minnesota), Barrier MIMD Architecture: Design and Compilation, 1990.
  3. Myong Hong Kang (Research Staff, NRL, Washington DC), Optimization and Parallelization of Database Queries, 1991.
  4. Yeun-Jyr Ju (Research Staff, AT&T, Middletown, NJ), Compiler Data Layout and Code Transformation for Reducing Cache Coherence Overhead, 1991.
  5. Menqiong Liou, Efficient Algorithms for Fractional Factorial Design Generation, 1992.
  6. Terence J. Parr (Founder & President, MageLang Institute), Obtaining Practical Variants of LL(k) and LR(k) for k>1, 1993.
  7. Chiiwen Liou , Compiler-Directed Cache Coherence for Multiprocessors, 1993.
  8. Eng-Siong Tan, Programming Plan Abstraction: A Cognitively Motivated Approach to Program Understanding Using Dependence Analysis, 1994
  9. William E. Cohen (Ass't Prof. of EE, U. of Alabama, Huntsville), Automatic Construction of Optimizing, Parallelizing Compilers from Specifications, 1994.
  10. Tai Myoung Chung (Ass't Prof. of ECE, SungKyunKwan University, Korea, CHaRTS: Compiler for Hard Real-Time Systems, 1995.

M.S. Thesis Students Graduated

  1. Michael J. Phillip (Motorola, Austin, TX), Unification of Synchronous and Asynchronous Models for Parallel Programming Languages, 1989.
  2. Terence J. Parr (Founder & President, MageLang Institute), The Analysis of Extended BNF Grammars and the Construction of LL(1) Parsers, 1990.
  3. Abderrazek Zaafrani, Static Scheduling of Barrier MIMD Architecture, 1990.
  4. Ashar Nisar (Tandem, Sunnyvale, CA), Optimal Code Scheduling for Multiple Pipeline Processors, 1990.
  5. Tariq Muhammad, Hardware Barrier Synchronization For A Cluster Of Personal Computers, 1995.

Ph.D. Students Being Supervised

Raymond Hoare
Aggregate function networks (PAPERS)
Randy Fisher
SIMD Within A Register (SWAR)
Soohong Peter Kim
VLIW using aggregate networks
Gayathri Krishnamurthy
Shared-memory parallel job scheduling
Philip Nwokah
Aggregate file I/O

M.S. Thesis Students Being Supervised

Timothy Mattox
Aggregate function networks (PAPERS)

Courses Developed/Upgraded at Purdue

EE363
Software Engineering: C Language
(Upgraded existing course)
EE468
Introduction to Compilers and Translation Engineering
EE469
Operating Systems Engineering
EE469L
Operating Systems Engineering Lab
EE495X,W,Z
Vertically Integrated Project Track,
EPICS: Engineering Projects In Community Service
(Co-Developed with E. J. Coyle and L. H. Jamieson)
EE563
Programming Parallel Machines
(Co-Developed with H. J. Siegel and J. L. Gray)
EE573
Compilers and Translator Writing Systems
EE663
Compiler Code Generation, Optimization, and Parallelization

Publications in Books, Journals, and Conferences

  1. H. G. Dietz and R. J Juels, "A Microprocessor Directed Multiprotocol Local Network," IEEE Proceedings of Micro DelCon, pp. 44-48, University of Delaware, 1983.
  2. H. G. Dietz and R. J Juels, "A Universal Computer Aided Instruction System," IEEE Proceedings of the National Educational Computing Conference, pp. 279-282, Baltimore, Maryland, June 1983.
  3. H. G. Dietz and R. J Juels, "A Computer Science Approach to Computer Aided Instruction Courseware Development," IEEE Proceedings of Ed CompCon '83, pp. 37-42, Silicon Valley, California, October 18-20, 1983.
  4. H. G. Dietz and R. J Juels, "Microcomputer Aided Instruction," Proceedings of the Twenty-Sixth International Society for Mini and Microcomputers (ISMM) International Symposium on Applications of Microcomputers, pp. 1-5, New York, New York, 1984.
  5. H. G. Dietz and R. J Juels, "Digital Halftone Techniques for Microcomputers," Proceedings of the Twenty-Seventh International Society for Mini and Microcomputers (ISMM) International Symposium on Microcomputer Applications in Medicine, pp. 89-93, New York, New York, 1984.
  6. H. G. Dietz and A. D. Klappholz, "Refining A Conventional Language for Race-Free Specification of Parallel Algorithms," IEEE Proceedings of the 1984 International Conference on Parallel Processing, pp. 380-382, Bellaire, Michigan, August 1984. (43% (89/205) accepted as full or short.)
  7. H. George Dietz and H. Gordon Dietz, "A Reliable, Inexpensive, Inhalation Sensor," Abstracts from the 11th Northeast Bioengineering Conference, p. 97, Worcester Polytechnic Institute, Worcester, Massachusetts, March 14-15, 1985.
  8. H. G. Dietz and A. D. Klappholz, "Refined C: A Sequential Language for Parallel Programming," IEEE Proceedings of the 1985 International Conference on Parallel Processing, pp. 442-449, St. Charles, Illinois, August 1985. (33% (82/251) accepted as full.)
  9. H. G. Dietz and A. D. Klappholz, "An Expert Tool for Programming Multiprocessors," Abstracts from the Second SIAM Conference on Parallel Processing for Scientific Computing, p. A21, Norfolk, Virginia, November 19, 1985.
  10. H. G. Dietz and A. D. Klappholz, "RISC CPU Design for MIMDs," Abstracts from the Second SIAM Conference on Parallel Processing for Scientific Computing, p. A27, Norfolk, Virginia, November 20, 1985.
  11. H. G. Dietz, K. Stein, and A. D. Klappholz, "Sequential Languages for Programming Highly-Parallel Computers," Abstracts from the Second SIAM Conference on Parallel Processing for Scientific Computing, p. A27, Norfolk, Virginia, November 21, 1985.
  12. H. G. Dietz and D. Mulcahy, "Romany of a Third Place: A Statistical Analysis of 19th Century Calo and Castilian," presented at the Eighth Annual Meeting of the Gypsy Lore Society, North American Chapter, New York, New York, February 1986. (Revised and re-reviewed version is other publication [1] listed above.)
  13. H. G. Dietz, A. D. Klappholz, Y-S. Liao, and K. Stein, "The Refined Language Methodology," Abstracts from the Sequential Languages for Parallel Supercomputers Minisymposium of the SIAM 1986 National Meeting, p. A11, Boston, Massachusetts, July 22, 1986.
  14. H. G. Dietz and A. D. Klappholz, "Refined FORTRAN: Another Sequential Language for Parallel Programming," IEEE Proceedings of the 1986 International Conference on Parallel Processing, pp. 184-191, Saint Charles, Illinois, August 1986. (24% (97/400) accepted as full.)
  15. H. G. Dietz and A. D. Klappholz, "The Refined Language Approach to Programming Parallel Machines," invited presentation at the NASA/ICASE Parallel Languages and Environments Workshop, November 12, 1986.
  16. D. Klappholz, H. G. Dietz, X. Kong, H.-C. Park, and K. Stein, "Refined languages: an evolutionary approach to the use of sequential languages for programming parallel (MIMD) machines," Parallel processing: State of the Art Report 15:4, edited by C. Jesshope, Pergamon Infotech, New York, 1987, pp. 59-70.
  17. T. L. Casavant, H. G. Dietz, T. Schwederski, C-Y. Sheu, and H. J. Siegel, "Software Plans for PASM," invited presentation and paper in Proceedings of the 2nd International Conference on Supercomputing, Volume 1, pp. 428-439, Santa Clara, California, May 1987.
  18. H. G. Dietz and T. Schwederski, "Barrier MIMD: Beyond VLIW," poster presented at the Third SIAM Conference on Parallel Processing for Scientific Computing, Los Angeles, California, December 1987.
  19. H. G. Dietz, "Parallelization of Arbitrary Loops," poster presented at the Third SIAM Conference on Parallel Processing for Scientific Computing, Los Angeles, California, December 1987.
  20. C-H. Chi and H. G. Dietz, "Compiler-Driven Cache Management," poster presented at the Third SIAM Conference on Parallel Processing for Scientific Computing, Los Angeles, California, December 1987.
  21. H. G. Dietz and D. Mulcahy, "Romany of a Third Place: A Statistical Analysis of 19th Century Calo and Castilian," Gypsy Lore Society, North American Chapter, Publications No. 4, 1988, pp. 1-17. (This publication consists of papers invited from the 8th and 9th annual meetings of the Gypsy Lore Society; papers were put through a second peer review before acceptance and publication. 48% (12/25) accepted.)
  22. H. G. Dietz and C-H. Chi, "A Compiler-Writer's View of GaAs Computer System Design," IEEE Proceedings of the 21st Hawaii International Conference on Systems Sciences, Architecture Track, vol. 1, pp. 256-265, January 1988.
  23. C-H. Chi and H. G. Dietz, "Register Allocation for GaAs Computer Systems," IEEE Proceedings of the 21st Hawaii International Conference on Systems Sciences, Architecture Track, vol. 1, pp. 266-274, January 1988. (One of two papers awarded "special honorary mention" for best paper.)
  24. H. G. Dietz, T. L. Casavant, and C-Y. Sheu, "PARSE: An Integrated Programming Environment for Non-Shared Memory, Reconfigurable, Parallel Computers," invited presentation at the Midwest Society for Programming Languages and Systems (MSPLS) Spring Meeting, April 30, 1988.
  25. H. G. Dietz, "Finding Large-Grain Parallelism in Loops with Serial Control Dependencies," Proceedings of the 1988 International Conference on Parallel Processing, vol. 2., pp. 114-121, Saint Charles, Illinois, August 1988. (13% (79/590) accepted as full.)
  26. H. G. Dietz and C-H. Chi, "CRegs: A New Kind of Memory for Referencing Arrays and Pointers," IEEE Proceedings of Supercomputing 1988, pp. 360-367, Orlando, Florida, November 1988.
  27. C-H. Chi and H. G. Dietz, "Improving Cache Performance by Selective Cache Bypass," IEEE Proceedings of the 22nd Hawaii International Conference on Systems Sciences, Architecture Track, vol. 1, pp. 256-265, January 1989.
  28. T. L. Casavant, H. G. Dietz, C-Y. Sheu, and H. J. Siegel, "The PARSE Approach to Programming Non-Shared Memory, Reconfigurable, Parallel Computers," invited presentation and paper in Proceedings of the Fourth International Conference on Supercomputing, vol. 1., pp. 380-389, Santa Clara, California, May 1989.
  29. M. J. Phillip and H. G. Dietz, "Toward Semantic Self- Consistency in Explicitly Parallel Languages," invited presentation and paper in Proceedings of the Fourth International Conference on Supercomputing, vol. 1., pp. 398-407, Santa Clara, California, May 1989.
  30. C-H. Chi and H. G. Dietz, "Unified Management of Registers and Cache Using Liveness and Cache Bypass," ACM Proceedings of the SIGPLAN 89 Conference on Programming Language Design and Implementation, pp. 344-355, Portland, Oregon, June 1989. (18% (31/171) accepted.)
  31. H. G. Dietz, T. Schwederski, M. T. O'Keefe, and A. Zaafrani, "Static Synchronization Beyond VLIW," IEEE Proceedings of Supercomputing 1989, pp. 416-425, Reno, Nevada, November 1989.
  32. H. G. Dietz, H. J. Siegel, W. E. Cohen, M. T. O'Keefe, et al., "A Compiler-Oriented Architecture: The CARP Machine," poster presented at the Fourth SIAM Conference on Parallel Processing for Scientific Computing, Chicago, Illinois, December 1989.
  33. H. G. Dietz, M. T. O'Keefe, and A. Zaafrani, "Eliminating Runtime Synchronizations by Static Barrier Scheduling," poster presented at the Fourth SIAM Conference on Parallel Processing for Scientific Computing, Chicago, Illinois, December 1989.
  34. L-Y. Chang and H. G. Dietz, "An Introduction to Compiler Optimization of Data Layout," poster presented at the Fourth SIAM Conference on Parallel Processing for Scientific Computing, Chicago, Illinois, December 1989.
  35. M. H. Kang and H. G. Dietz, "Algorithm Choice for Multiple-Query Evaluation," IEEE Proceedings of PARBASE-90, 1 page, Miami, Florida, July 1990. (<=67% accepted as full or short.)
  36. M. T. O'Keefe and H. G. Dietz, "Hardware Barrier Synchronization: Dynamic Barrier MIMD (DBM)," Proceedings of the 1990 International Conference on Parallel Processing, vol. I, pp. 43-45, Saint Charles, Illinois, August 1990. (35% (191/546) accepted as full or short.)
  37. M. T. O'Keefe and H. G. Dietz, "Hardware Barrier Synchronization: Static Barrier MIMD (SBM)," Proceedings of the 1990 International Conference on Parallel Processing, vol. I, pp. 35-42, Saint Charles, Illinois, August 1990. (16% (86/546) accepted as full.)
  38. A. Zaafrani, H. G. Dietz, and M. T. O'Keefe, "Static Scheduling for Barrier MIMD Architectures," Proceedings of the 1990 International Conference on Parallel Processing, vol. II, pp. 187-194, Saint Charles, Illinois, August 1990. (16% (86/546) accepted as full.)
  39. A. Nisar and H. G. Dietz, "Optimal Code Scheduling for Multiple Pipeline Processors," Proceedings of the 1990 International Conference on Parallel Processing, vol. II, pp. 61-64, Saint Charles, Illinois, August 1990. (35% (191/546) accepted as full or short.)
  40. M. Nichols, H. J. Siegel, H. G. Dietz, R. W. Quong, and W. G. Nation, "Minimizing Memory Requirements for Partitionable SIMD/SPMD Machines," Proceedings of the 1990 International Conference on Parallel Processing, vol. I, pp. 84-91, Saint Charles, Illinois, August 1990. (16% (86/546) accepted as full.)
  41. H. G. Dietz, M. T. O'Keefe, and A. Zaafrani, "An Introduction to Static Scheduling for MIMD Architectures," Proceedings of the Third Workshop on Programming Languages and Compilers for Parallel Computing, pp. 1-26, Irvine, California, August 1990. (Revised version is book chapter [2] listed above.)
  42. M. A. Nichols, H. J. Siegel, and H. G. Dietz, "Data Management and Control-Flow Aspects of an SIMD/SPMD Parallel Language/Compiler," IEEE Proceedings of the Frontiers '90: The Third Symposium on the Frontiers of Massively Parallel Computation, pp. 397-406, October 1990. (26% (39/152) accepted as full.)
  43. T. J. Parr, W. E. Cohen, and H. G. Dietz, "PCCTS and LL(K) Parser Generation," invited presentation at the Midwest Society for Programming Languages and Systems (MSPLS) Fall Meeting, University of Illinois at Chicago Circle, Chicago, Illinois, November 10, 1990.
  44. H. G. Dietz, M. T. O'Keefe, A. Zaafrani, "An Introduction to Static Scheduling for MIMD Architectures," Advances in Languages and Compilers for Parallel Processing, edited by A. Nicolau, D. Gelernter, T. Gross, and D. Padua, The MIT Press, Cambridge, Massachusetts, 1991, pp. 425-444. (Also published by Pitman, London, 1991.)
  45. H. G. Dietz, "Portability Through Transformability," invited presentation also in the Proceedings of The Ohio State University Second Workshop on Parallel Computing (Tools, Techniques and Environments for the Development of Parallel Programs), Columbus, Ohio, March 1991.
  46. H. G. Dietz, "Common Subexpression Induction," invited presentation at the Midwest Society for Programming Languages and Systems (MSPLS) Spring Meeting, Digital Computer Laboratory (DCL), University of Illinois at Urbana- Champaign, Urbana, Illinois, April 20, 1991.
  47. M. A. Nichols, H. J. Siegel, H. G. Dietz, R. Quong, and W. Nation, "Eliminating Memory Fragmentation Within Partitionable SIMD/SPMD Machines," IEEE Transactions on Parallel and Distributed Systems, vol. 2, no. 3, pp. 290-303, July 1991.
  48. Y-J. Ju and H. G. Dietz, "Reduction of Cache Coherence Overhead by Compiler Data Layout and Loop Transformation," Proceedings of the Fourth Workshop on Programming Languages and Compilers for Parallel Computing, pp. Q1-Q15, Santa Clara, California, August 1991.
  49. M. A. Nichols, H. J. Siegel, and H. G. Dietz, "Execution Mode Management and CU/PE Overlap in an SIMD/SPMD Parallel Language/Compiler," IEEE Proceedings of the Computer Software and Applications Conference (COMPSAC '91), pp. 392-397, Tokyo, Japan, September 1991. (40% (100/249) accepted.)
  50. M. Liou, H. G. Dietz, H. Moskowitz, and R. Plante, "A New Algorithm for Two-Level RFFD Generation," IEEE Proceedings of the Portland International Conference on Management of Engineering and Technology (PICMET) 1991, pp. 328-331, Portland, Oregon, October 1991.
  51. M. Liou, H. G. Dietz, H. Moskowitz, and R. Plante, "A New Algorithm for IFFD Generation," IEEE Proceedings of the Portland International Conference on Management of Engineering and Technology (PICMET) 1991, pp. 332-334, Portland, Oregon, October 1991.
  52. Y-J. Ju and H. G. Dietz, "Reduction of Cache Coherence Overhead by Compiler Data Layout and Loop Transformation," Languages and Compilers for Parallel Computing, edited by U. Banerjee, D. Gelernter, A. Nicolau, and D. Padua, Springer- Verlag, New York, New York, 1992, pp. 344-358.
  53. H. G. Dietz, M. T. O'Keefe, and A. Zaafrani, "Static Scheduling for Barrier MIMD Architectures," The Journal of Supercomputing, vol. 5, pp. 263-289, 1992.
  54. T. J. Parr, H. G. Dietz, and W. E. Cohen, "PCCTS Reference Manual (version 1.00)," ACM SIGPLAN Notices, Feb. 1992, pp. 88-165.
  55. H. G. Dietz, "Common Subexpression Induction," Proceedings of the 1992 International Conference on Parallel Processing, vol. II, pp. 174-182, Saint Charles, Illinois, August 1992. (23% (28/121) accepted as full.)
  56. H. G. Dietz and W. E. Cohen, "A Control-Parallel Programming Model Implemented On SIMD Hardware," Conference Record of the Fifth Workshop on Programming Languages and Compilers for Parallel Computing, pp. 191-204, Yale University, August 1992.
  57. H. G. Dietz and W. E. Cohen, "A Control-Parallel Programming Model Implemented On SIMD Hardware," Languages and Compilers for Parallel Computing, edited by U. Banerjee, D. Gelernter, A. Nicolau, and D. Padua, Springer-Verlag, New York, New York, 1993, pp. 311-325.
  58. M. A. Nichols, H. J. Siegel, and H. G. Dietz, "Data Management and Control-Flow Aspects of an SIMD/SPMD Parallel Language," IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 2, pp. 222-234, February 1993.
  59. H. G. Dietz, W. E. Cohen, and B. K. Grant, "Would You Run It Here... Or There? (AHS: Automatic Heterogeneous Supercomputing)," Proceedings of the 1993 International Conference on Parallel Processing, vol. II, pp. 217-222, Saint Charles, Illinois, August 1993. (36% (55/154) accepted as concise or full.)
  60. H. G. Dietz and G. Krishnamurthy, "Meta-State Conversion," Proceedings of the 1993 International Conference on Parallel Processing, vol. II, pp. 47-56, Saint Charles, Illinois, August 1993. (10% (16/154) accepted as full.)
  61. H. G. Dietz and H. J. Siegel, "Purdue University Research Toward a Virtual Machine Programming Model for High- Performance Computing," Rome Laboratory Workshop on Virtual Machine Concepts, Rome Laboratory, Rome, NY, October 1993.
  62. H. G. Dietz, W. E. Cohen, T. Muhammad, and T. I. Mattox, "Compiler Techniques for Fine-Grain Execution on Workstation Clusters Using PAPERS," Languages and Compilers for Parallel Computing, edited by K. Pingali, U. Banerjee, D. Gelernter, A. Nicolau, and D. Padua, Springer-Verlag, New York, New York, 1994, pp. 31-45
  63. M. H. Kang, H. G. Dietz, and B. Bhargava, "Multiple-Query Optimization at Algorithm Level," Journal of Data and Knowledge Engineering, vol. 14, pp. 57-75, 1994.
  64. H. G. Dietz, W. E. Cohen, T. Muhammad, and T. I. Mattox, "Compiler Techniques for Fine-Grain Execution on Workstation Clusters Using PAPERS," Conference Record of the Seventh International Workshop on Programming Languages and Compilers for Parallel Computing, Cornell University, August 1994.
  65. W. E. Cohen, H. G. Dietz, and J. B. Sponaugle, "Dynamic Barrier Architecture for Multi-Mode Fine-Grain Parallelism Using Conventional Processors," Proceedings of the 1994 International Conference on Parallel Processing, vol. I, pp. 93-96, Saint Charles, Illinois, August 1994. (35% (68/195) accepted as concise or full.)
  66. J. B. Armstrong, H. J. Siegel, W. E. Cohen, M. Tan, H. G. Dietz, and J. A. B. Fortes, "Dynamic Task Migration from SPMD to SIMD Virtual Machines," Proceedings of the 1994 International Conference on Parallel Processing, vol. II, pp. 160-169, Saint Charles, Illinois, August 1994. (14% (16/118) accepted as full.)
  67. M. O'Keefe, T. Parr, B. K. Edgar, S. Anderson, P. Woodward, and H. G. Dietz, "The Fortran-P Translator: Towards Automatic Translation of Fortran 77 Programs for Massively Parallel Processors," John Wiley and Sons, Inc., Scientific Programming, vol. 4, pp. 1-21, 1995.
  68. T. M. Chung and H. G. Dietz, "Language Constructs for High-Precision Specification of Real Time Constraints," Midwest Society for Programming Languages and Systems (MSPLS) Spring Meeting, Purdue University, West Lafayette, Indiana, April 8, 1995.
  69. H. G. Dietz, T. M. Chung, and T. I. Mattox, "A Parallel Processing Support Library Based On Synchronized Aggregate Communication," 1995 Workshop on Languages and Compilers for Parallel Computing, Ohio State University, Ohio, August 1995.
  70. W. E. Cohen and H. G. Dietz, "A Data-Parallel Language on Purdue's Adapter for Parallel Execution and Rapid Synchronization," Midwest Society for Programming Languages and Systems (MSPLS) Fall Meeting, Loyola University, Chicago, Illinois, October 28, 1995.
  71. H. G. Dietz, "A New Type Of Electronic Journal," Midwest Society for Programming Languages and Systems (MSPLS) Fall Meeting, Loyola University, Chicago, Illinois, October 28, 1995.
  72. H. G. Dietz, T. M. Chung, and T. I. Mattox, "A Parallel Processing Support Library Based On Synchronized Aggregate Communication," Languages and Compilers for Parallel Computing, edited by C.-H. Huang, P. Sadayappan, U. Banerjee, D. Gelernter, A. Nicolau, and D. Padua, Springer- Verlag, New York, New York, 1996, pp. 254-268.
  73. H. J. Siegel, H. G. Dietz, and J. Antonio, "Software Support for Heterogeneous Computing," ACM Computing Surveys, Vol. 28, No. 1, pp. 237-239, March 1996.
  74. H. J. Siegel, T. Braun, H. G. Dietz, M. B. Kulaczewski, M. Maheswaran, P. H. Pero, J. M. Siegel, J. J. E. So, M. Tan, M. D. Theys, and L. Wang, "The PASM Project: A Study of Reconfigurable Parallel Computing," 2nd International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN '96), sponsor: Chinese National Research Center for Intelligent Computing Systems (NCIC), pp. 529-536, Beijing, China, June 1996.
  75. H. G. Dietz, E. J. Coyle, and L. H. Jamieson, "Long-Term Community Service Projects in the Purdue Engineering Curriculum," Proceedings of the 1996 ASEE Annual Conference, Washington, D.C., June 1996.
  76. H. G. Dietz, R. Hoare, and T. Mattox, "A Fine-Grain Parallel Architecture Based On Barrier Synchronization," Proceedings of the 1996 International Conference on Parallel Processing, vol. I, pp. 247-250, Bloomington, Illinois, August 1996. (33% (71/270) accepted as concise or full.)
  77. R. Hoare, H. Dietz, T. Mattox, and S. Kim, "Bitwise Aggregate Networks," In Proceedings of The Eighth IEEE Symposium on Parallel and Distributed Processing (SPDP'96), New Orleans, Louisiana, October 1996.
  78. H. J. Siegel, H. G. Dietz, and J. Antonio, "Software Support for Heterogeneous Computing," in The Computer Science and Engineering Handbook, edited by Allen B. Tucker, Jr., CRC Press, Boca Raton, FL, pp. 1886-1909, 1997.
  79. H. G. Dietz and T. I. Mattox, "Managing Polyatomic Coherence and Races with Replicated Shared Memory," to appear in the special issue on DSM (distributed shared memory) and related issues, IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, pp. 53-58, April 1997.
  80. S. Kim and H. G. Dietz, "VLIW-Style Parallelism On Aggregate Function Clusters," to appear in IEEE Technical Committee on Computer Architecture (TCCA) Newsletter, July 1997.
  81. S. Kim and H. G. Dietz, "VLIW-Style Parallelism On Aggregate Function Clusters," Workshop on Interaction between Compilers and Computer Architectures, San Antonio, Texas, February 1997.

Technical Reports

  1. TR-EE 87-21, Compiler-Driven Cache Policy (Known Reference String), C-H. Chi and H. G. Dietz, June 1987, 54 pages.
  2. TR-EE 87-22, The PARSE Programming Paradigm, The PARSE Group (T. L. Casavant, H. G. Dietz, C-Y. Sheu, and H. J. Siegel), February 1987, 58 pages.
  3. TR-EE 87-29, Processor Design Guidelines for MIMDs, H. G. Dietz, September 1987, 17 pages.
  4. TR-EE 87-30, Loop Parallelization by Selective Serialization, H. G. Dietz, September 1987, 12 pages.
  5. TR-EE 87-31, Optimal Register Allocation Using a State Transition Model, C-H. Chi and H. G. Dietz, September 1987, 25 pages.
  6. TR-EE 88-25, Extending Static Synchronization Beyond SIMD and VLIW, H. G. Dietz and T. Schwederski, June 1988, 24 pages.
  7. TR-EE 88-36, Improving Cache Performance by Selective Cache Bypass, C-H. Chi and H. G. Dietz, July 1988, 22 pages.
  8. TR-EE 89-50, Algorithm Choice for Multiple-Query Evaluation, M. H. Kang and H. G. Dietz, August 1989, 20 pages.
  9. TR-EE 89-51, Performance Analysis of Hardware Barrier Synchronization, M. T. O'Keefe and H. G. Dietz, August 1989, 20 pages.
  10. SERC-TR-50-P, Toward Semantic Self-Consistency in Explicitly Parallel Languages, M. J. Phillip and H. G. Dietz, August 1989, 10 pages.
  11. SERC-TR-51-P, The PARSE Approach to Programming Non-Shared Memory, Reconfigurable, Parallel Computers, T. L. Casavant, H. G. Dietz, C-Y. Sheu, and H. J. Siegel, August 1989, 10 pages.
  12. TR-EE 89-71, Compiler-Driven Cache Management Using a State Level Transition Model, C-H. Chi (revised version of Ph.D. thesis supervised by H. G. Dietz), December 1989, 246 pages.
  13. TR-EE 90-7, Automatic Parallelization of Database Queries, M. H. Kang and H. G. Dietz, January 1990, 22 pages.
  14. TR-EE 90-8, Hardware Barrier Synchronization: Static Barrier MIMD (SBM), M. T. O'Keefe and H. G. Dietz, January 1990, 26 pages.
  15. TR-EE 90-9, Hardware Barrier Synchronization: Dynamic Barrier MIMD (DBM), M. T. O'Keefe and H. G. Dietz, January 1990, 27 pages.
  16. TR-EE 90-10, Static Scheduling for Barrier MIMD Architectures, A. Zaafrani, H. G. Dietz, and M. T. O'Keefe, January 1990, 25 pages.
  17. TR-EE 90-11, Optimal Code Scheduling for Multiple-Pipeline Processors, A. Nisar and H. G. Dietz, January 1990, 23 pages.
  18. TR-EE 90-14, Purdue Compiler-Construction Tool Set, T. J. Parr, H. G. Dietz, and W. E. Cohen, February 1990, 77 pages.
  19. TR-EE 90-30, The Analysis of Extended BNF Grammars and the Construction of LL(1) Parsers, T. J. Parr (reprint of M.S. thesis supervised by H. G. Dietz), May 1990, 87 pages.
  20. TR-EE 90-41, A Simple Vector Language and its Portable Implementation, A. Jhaveri and H. G. Dietz, May 1990, 44 pages.
  21. TR-EE 90-42, Optimal Code Scheduling for Multiple-Pipeline Processors, A. Nisar (reprint of M.S. thesis supervised by H. G. Dietz), May 1990, 83 pages.
  22. TR-EE 90-43, Data Layout Optimization and Code Transformation for Paged Memory Systems, L-Y. Chang and H. G. Dietz, April 1990, 21 pages.
  23. TR-EE 90-44, Loop Coalescing and Scheduling for Barrier MIMD Architectures, M. T. O'Keefe and H. G. Dietz, June 1990, 31 pages.
  24. UMSI 91/330, Fortran-P, H. G. Dietz, M. T. O'Keefe, T. J. Parr, T. Varghese, and P. R. Woodward, University of Minnesota Supercomputer Institute Research Report, December 1991, 14 pages.
  25. TR-EE 92-4, A Massively Parallel MIMD Implemented by SIMD Hardware, H. G. Dietz and W. E. Cohen, January 1992, 26 pages.
  26. TR-EE 92-5, Common Subexpression Induction, H. G. Dietz, January 1992, 24 pages.
  27. TR-EE 92-30, A Practical Approach To LL(k): LLM(N), T. J. Parr and H. G. Dietz, July 1992, 34 pages.
  28. TR-EE 92-31, Coding Multiway Branches Using Customized Hash Functions, H. G. Dietz, July 1992, 28 pages.
  29. TR-EE 93-4, Compiler-Assisted Cache Coherence, Chiiwen Liou and H. G. Dietz, January 1993, 23 pages.
  30. TR-EE 93-5, Would You Run It Here... Or There? (AHS: Automatic Heterogeneous Supercomputing), H. G. Dietz, W. E. Cohen, and B. K. Grant, January 1993.
  31. TR-EE 93-6, Meta-State Conversion, H. G. Dietz, January 1993.
  32. AHPCRC 93-021, M. T. O'Keefe, T. J. Parr, B. K. Edgar, P. Woodward, and H. G. Dietz, "The Fortran-P Translator: Automatic Translation of Fortran 77 Programs for Massively Parallel Processors," Army High Performance Computing Research Center Preprint, February 1993.
  33. TR-EE 94-9, Dynamic Barrier Architecture For Multi-Mode Fine-Grain Parallelism Using Conventional Processors; Part I: Barrier Architecture, W. E. Cohen, H. G. Dietz, and J. B. Sponaugle, March 1994.
  34. TR-EE 94-10, Dynamic Barrier Architecture For Multi-Mode Fine-Grain Parallelism Using Conventional Processors; Part II: Mode Emulation, W. E. Cohen, H. G. Dietz, and J. B. Sponaugle, March 1994.
  35. TR-EE 94-11, PAPERS: Purdue's Adapter for Parallel Execution and Rapid Synchronization, H. G. Dietz, T. Muhammad, J. B. Sponaugle, and T. Mattox, March 1994.
  36. RL-TR-94-221, G. C. Fox, S. Hariri, H. J. Siegel, H. G. Dietz, and C. V. Ramamoorthy, "Rome Laboratory Software Engineering Cooperative Virtual Machine," Rome Laboratory, Air Force Materiel Command, Griffiss Air Force Base, NY, Technical Report No. RL-TR-94-221, December 1994, 67 pages.
  37. http://garage.ecn.purdue.edu/~papers/PS/super4.ps.Z
    "TTL Implementation of Purdue's Adapter for Parallel Execution and Rapid Synchronization," H. G. Dietz, T. Muhammad, and T. I. Mattox, December 1994.
  38. http://garage.ecn.purdue.edu/~papers/ICPP95/paper.html
    "Purdue's Adapter for Parallel Execution and Rapid Synchronization: The TTL_PAPERS Design," H. G. Dietz, T. M. Chung, T. Muhammad, and T. I. Mattox, January 1995.
  39. http://dynamo.ecn.purdue.edu/~hankd/CARP/GENROUTE/paper.html
    "Genetic Scheduling of Router Operations for the MasPar MP-1/MP-2," H. G. Dietz and T. M. Chung. January 1995.
  40. http://garage.ecn.purdue.edu/~papers/ICPP95/paper.html
    "Purdue's Adapter for Parallel Execution and Rapid Synchronization: The TTL_PAPERS Design," H. G. Dietz, T. M. Chung, T. I. Mattox, and T. Muhammad, January 1995.
  41. http://garage.ecn.purdue.edu/~papers/LIB/paper.html
    "A Synchronization and Aggregate Communication Library for PAPERS Clusters," H. G. Dietz, T. M. Chung, T. Mattox, and T. Muhammad, January 1995.
  42. http://dynamo.ecn.purdue.edu/~hankd/CHaRTS/lang.ps.Z
    "Language Constructs and Transformation for Hard Real-Time Systems," T. M. Chung and H. G. Dietz, February 1995.
  43. http://garage.ecn.purdue.edu/~papers/MUSEUM/history.html
    "The PAPERS Museum," H. G. Dietz, March 1995.
  44. http://dynamo.ecn.purdue.edu/~hankd/CARPVIEW/Index.html
    "What Is Compiler-Oriented Architecture?" H. G. Dietz, July 1995.
  45. http://garage.ecn.purdue.edu/~papers/giveioperm.html
    "The giveioperm() Function," G. Krishnamurthy and H. G. Dietz, November 1995.
  46. http://yara.ecn.purdue.edu/~pplinux/pphowto.html
    "Linux Parallel Processing HOWTO," H. G. Dietz, March 1996.
  47. http://dynamo.ecn.purdue.edu/~hankd/Opinions/pardead.html
    "Is Parallel Processing Dead?" H. G. Dietz, June 6, 1996.
  48. http://dynamo.ecn.purdue.edu/~hankd/SWAR/over.html
    "Technical Summary: SWAR Technology," H. G. Dietz, February 1997.

Conference Tutorials

  1. H. G. Dietz, "High-Performance Parallel Processing Using PCs and Linux," full day tutorial at the 25th International Conference on Parallel Processing, Bloomington, IL, August 16, 1996.
  2. H. G. Dietz, "Parallel Processing Architectures Using PCs And Linux," half day tutorial at the IEEE/ACM 1997 International Symposium on Computer Architecture (ISCA97), to be held June 1, 1997.

Invited Lectures

  1. H. G. Dietz, "Digital Halftone Techniques," invited lecture presentation at IBM Watson Research Center, Yorktown, New York, March 20, 1986.
  2. H. G. Dietz, "Extending Static Synchronization Beyond VLIW," Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, Urbana, Illinois, October 23, 1989.
  3. H. G. Dietz, "An Overview of PARSE - A Parallel Software Environment," Software Engineering Research Center (SERC), Purdue University, West Lafayette, Indiana, January 31, 1990.
  4. H. G. Dietz, "Compiler-oriented Architecture," Computer Science Seminar, Carnegie-Mellon University, Pittsburgh, Pennsylvania, March 8, 1990.
  5. H. G. Dietz, "Extending Static Synchronization Beyond VLIW," Thinking Machines Corporation, Cambridge, Massachusetts, April 17, 1990.
  6. H. G. Dietz, "Making Different Operations Use The Same Instruction Sequence to Improve SIMD Performance," AHPCRC Colloquium, Army High-Performance Computing Center, Minneapolis, Minnesota, June 25, 1991.
  7. H. G. Dietz, "PE's for Nothin' and Your GIPS for Free," IEEE Computer Society Student Chapter, Purdue University, West Lafayette, Indiana, November 18, 1991.
  8. H. G. Dietz, "Common Subexpression Induction," MasPar Corporation, Sunnyvale, California, March 2, 1992.
  9. H. G. Dietz, "The MasPar MP-1 Is A MIMD?," MasPar Corporation, Sunnyvale, California, March 3, 1992.
  10. H. G. Dietz, "Fortran-P," AHPCRC Research Advisory Committee, Army High-Performance Computing Center, Minneapolis, Minnesota, March 11, 1992.
  11. H. G. Dietz, Panelist on "Instruction Level Parallelism," ONR Compiler Workshop, August 6, 1992.
  12. H. G. Dietz, "Compiler Techniques for MIMD Code on SIMD Hardware," Computer Science Seminar, Kent State University, Kent, Ohio, October 9, 1992.
  13. H. G. Dietz, Panelist on "How Much Better Can Compilers for Parallel Machines Get?" Fourth Symposium on the Frontiers of Massively-Parallel Computation, sponsored by the IEEE Computer Society, October 20, 1992.
  14. H. G. Dietz, "Overview Of The Cyclone Compiler Effort," Los Alamos National Laboratory, Los Alamos, New Mexico, December 3-4, 1992.
  15. H. G. Dietz, "Construction of Optimizing and Parallelizing Compilers from Language and Machine Descriptions," The International Workshop on Languages and Compilers for Parallel Computing, Sponsored by the Israeli Ministry of Science and Technology, Kibbutz Maale Hachamisha, Israel, June 2, 1993.
  16. H. G. Dietz, Panelist on "The Virtual Heterogeneous Supercomputer: Can It Be Built?" Second International Symposium on High Performance Distributed Computing (HPDC-2), July 21, 1993.
  17. H. G. Dietz, "Parallel Processing and the PPL MasPar," Civil Engineering, Purdue University, August 13, 1993.
  18. H. G. Dietz, Panelist on "Program Portability Across Parallel Architectures," IEEE 8th International Parallel Processing Symposium, April 28, 1994.
  19. H. G. Dietz, "What is Compiler-Oriented Architecture?" first talk in series "Compiler-Oriented Architecture For A 64-Bit Microprocessor To Be Used In Parallel Computers," Electronics and Telecommunications Research Institute (ETRI), Dae Jeon, Korea, October 17, 1994.
  20. H. G. Dietz, "What Should Your Compiler Do For You?" second talk in series "Compiler-Oriented Architecture For A 64-Bit Microprocessor To Be Used In Parallel Computers," Electronics and Telecommunications Research Institute (ETRI), Dae Jeon, Korea, October 18, 1994.
  21. H. G. Dietz, "Multiprocessor System Architecture" third talk in series "Compiler-Oriented Architecture For A 64-Bit Microprocessor To Be Used In Parallel Computers," Electronics and Telecommunications Research Institute (ETRI), Dae Jeon, Korea, October 19, 1994.
  22. H. G. Dietz, "Processor Architecture" fourth talk in series "Compiler-Oriented Architecture For A 64-Bit Microprocessor To Be Used In Parallel Computers," Electronics and Telecommunications Research Institute (ETRI), Dae Jeon, Korea, October 20, 1994.
  23. H. G. Dietz, "An Introduction To PAPERS And Cluster-Based Parallel Processing," Department of Electrical and Computer Engineering, University of Cincinatti, March 10, 1995.
  24. H. G. Dietz, "Portability Through Transformability," panelist on "SPMD: on a collision course with portability?" 1995 International Conference on Parallel Processing, August 15, 1995.
  25. H. G. Dietz, "What A Little Global Information Can Do For Parallel Processing," Department of Electrical Engineering, University of Alabama at Huntsville, Alabama, October 9, 1995.
  26. H. G. Dietz, "An Overview Of Parallel Processing," Bucknell University, Lewisburg, PA, November, 1995.
  27. H. G. Dietz, "Making A Lot Of Linux PCs Into A Parallel Supercomputer," NASA AMES Laboratories, Moutainview, CA, January 6, 1997.
  28. H. G. Dietz, "Multimedia Extensions For Microprocessors: SIMD Within A Register," Purdue University School of Electrical and Computer Engineering, Parallel Processing Seminar, February 13, 1997.
  29. H. G. Dietz, "Parallel Supercomputing Using PCs?" jointly sponsored by the Departments of Computer Science and Electrical Engineering, Washington University, St. Louis, MO, March 12, 1997.
  30. H. G. Dietz, "Parallel Processing Using Linux PCs: What Is And Isn't There," Pentium Pro Cluster Workshop, sponsored by the Scalable Computing Lab, Ames Laboratory/ISU, Des Moines, Iowa, April 10, 1997.

Conference Research Exhibits

  1. H. G. Dietz. Live demonstration of 4-processor PAPERS cluster of 486 PCs, 1994 International Conference on Parallel Processing, Saint Charles, Illinois, August 1994. Approximately 300 attendees.
  2. H. G. Dietz. 20'x20' formal research exhibit booth awarded for live demonstrations of four PAPERS clusters: 4-processor clusters of 486 PCs, IBM PowerPCs, and DEC Alpha Workstations and an 8-processor cluster of 386 PCs. The PowerPCs and Alphas were provided by IBM and DEC specifically for our exhibit. We also demonstrated the NSF- funded work (with G. B. Adams III) integrating compiler construction and architecture simulation. IEEE/ACM Supercomputing 1994, Washington D.C., November 1994. Approximately 6,000 attendees.
  3. H. G. Dietz. Live demonstrations of 2-processor PAPERS cluster and VAPERS using two laptop computers at 1995 Workshop on Languages and Compilers for Parallel Computing, Ohio State University, Ohio, August 12, 1995. Approximately 50 attendees.
  4. H. G. Dietz. Live demonstrations of 2-processor PAPERS cluster and VAPERS using two laptop computers at 1995 International Conference on Parallel Processing, Saint Charles, Illinois, August 1995. Approximately 300 attendees.
  5. H. G. Dietz. 20'x10' formal research exhibit booth awarded for live demonstrations of two PAPERS clusters: 4-processor clusters of 486 PCs and laptops, also demonstrated as a heterogeneous 8-processor cluster. We also demonstrated the NSF-funded work (with G. B. Adams III) integrating compiler construction and architecture simulation. IEEE/ACM Supercomputing 1995, San Diego, CA, December 1995. More than 5,000 attendees.
  6. H. G. Dietz. Live demonstrations of 4-processor PAPERS/Ethernet cluster (PAPERS AFAPI, PVM, and MPI) and a dual-processor Pentium 100 system (SHMAPERS AFAPI) at the 25th International Conference on Parallel Processing, Bloomington, IL, August 1996. Approximately 300 attendees.
  7. H. G. Dietz. 20'x20' formal research exhibit booth awarded for live demonstrations of PAPERS clusters with VGA video walls, the new AFAPI libraries, the CASLE software, and a small display showing the history of parallel processing at Purdue ECE (for the ACM 50th anniversary). In total, our booth included 37 separate machines and 27 monitors, which we believe was more than any other single exhibit. The demonstrations range from a cluster of four compact laptops to a large 16-machine VGA video wall; there were even two DEC Alpha systems loaned to us explicitly for the exhibit. IEEE/ACM Supercomputing 1996, Pittsburgh, PA, November 1996. About 5,000 attendees.
  8. H. G. Dietz. Live demonstrations of the 4-machine TTL_PAPERS microCluster at the DOE Pentium Pro Cluster Workshop, Des Moines, IA, April 9-11, 1997. About 50 attendees.

Major Software Releases

  1. http://dynamo.ecn.purdue.edu/~hankd/PCCTS/ http://java.magelang.com/antlr/entry.html
    PCCTS (the Purdue Compiler-Construction Tool Set) is a public-domain set of software tools for building compilers. First released in Spring 1990, it is now in use at tens of thousands of sites worldwide, including many companies (NeXT, SGI, etc.) and universities; see the statistics info linked to the home page. PCCTS has also spawned a network news group, comp.compilers.pccts, and a company, Parr Research Incorporated. As of 1997, there is also a textbook about PCCTS.
  2. http://garage.ecn.purdue.edu/~papers/SOFTWARE/Index.html
    TTL_VAPERS/TTL_PAPERS (Virtual Adapter for Parallel Execution and Rapid Synchronization and Purdue's Adapter for Parallel Execution and Rapid Synchronization) library release. First released in June 1995, this library provides both a simulated and a hardware-based parallel computing environment for PCs/workstations under unix. In early 1996, we knew of six other research sites and two companies that have replicated our hardware; we do not know how many sites use the software simulator.
  3. http://garage.ecn.purdue.edu/~papers/AFAPI/Index.html
    AFAPI (Aggregate Function Application Program Interface) not only upgrades and replaces the TTL_VAPERS/TTL_PAPERS library, but also establishes a portable standard API for aggregate communication operations. First released in mid 1996, there are actually three entirely separate implementations of the AFAPI, each targeting different hardware. The CAPERS AFAPI targets two-machine clusters connected by a (LapLink) cable, TTL_PAPERS AFAPI targets various size clusters connected using TTL_PAPERS hardware, and SHMAPERS AFAPI targets uniprocessor systems and shared-memory multiprocessors supporting UNIX System V IPC shared memory segments. In early 1997, there are at least a dozen sites playing with the TTL_PAPERS AFAPI; we do not know how many users there are for CAPERS or SHMAPERS.
  4. http://purcell.ecn.purdue.edu/~casle/Index.html
    CASLE (Compiler/Architecture Simulation for Learning and Experimenting) was co-developed with Prof. G. B. Adams III. It provides an HTML forms-interface tool set that will automatically produce an optimizing compiler, assembler, and architectural simulator using the specified architecture and compiler technology. Thus, undergraduate and graduate students can experiment with the total-system effect of changing the number of registers, instruction latencies, optimizations used, etc.
  5. http://yake.ecn.purdue.edu/~icpp/
    This site contains an extensive set of WWW and email server scripts which together implement full electronic submission and reviewing for the 26th International Conference on Parallel Processing (ICPP97), to be held August 11-15, 1997, Bloomington, IL. I created ICPP's first WWW site for ICPP96; as the Program Chairman for ICPP97, it was clear to me that electronic submission would be needed, and also that existing servers would not be satisfactory. The server system that I created incorporates a variety of innovations, and, at the request of several other conference program committees, a (slightly revised and more generic version) will be made available as a full public domain release in mid 1997. This server will also be used for the upcoming fully peer-reviewed MSPLS electronic journal.

Research Grants, Contracts, and Donations

  1. Principal Investigator: research in digital halftoning techniques for display of medical images, Polytechnic Institute of New York, funded by DuPont (~$70K). 1984-1986.
  2. Consultant: led feasibility study toward implementing a "Refined Fortran" compiler and implementation effort for a "Refined C" compiler, Stevens Institute of Technology, Center for Distributed Systems (Fortran work funded by Perkin Elmer, ~$60K; C work funded by IBM Watson, ~$250K). 1985-1986.
  3. With T. Schwederski, obtained donation of 16-processor Inmos Transputer development system (~$30K). 1987.
  4. Principal Investigator: "PARSE -- a PARallel Software Environment," funded through the Software Engineering Research Center (SERC) under National Science Foundation (NSF) award number 8624385A3-CDR ($69K). June 15, 1988 - March 14, 1991.
  5. Participant (principal investigator: H. J. Siegel): "Infrastructure for Parallel Processing," National Science Foundation (NSF) award number 9015696-CDA (~$1.4M). January 1, 1991 - December 31, 1995.
  6. Principal Investigator: "Compiler-Oriented Architecture," Office of Naval Research (ONR) grant number N00014-91-J-4013 ($225K). September 1, 1991 - August 31, 1994.
  7. From the Army High-Performance Computing Research Center (AHPCRC), Minneapolis, MN. Obtained access to AHPCRC supercomputer facilities, including a Thinking Machines CM2. Also given support for a student to do Ph.D. work under me as an "HPC Graduate Fellow" (~$20K). 1991 - 1992.
  8. Principal Investigator: "Development of a Cyclone Fortran-P Compiler," IBM, Austin, Texas ($48K). May 11, 1992 - August 14, 1992.
  9. Co-Principal Investigator (co-principal investigator: H. J. Siegel): "A Virtual Machine Programming Model For High-Performance Computing," United States Air Force (USAF) Rome Laboratories award number F30602-92-C-0150 ($30K). September 1, 1992 - August 31, 1993.
  10. Co-Principal Investigator (co-principal investigator: G. B. Adams III): "Compiler and Architecture Software Tools," National Science Foundation (NSF) award number CDA-9312649 (~$402K). August 15, 1993 - August 14, 1996.
  11. Principal Recipient: Motorola, PowerPC processors donation ($5K) in support of the CARDBoard (Compiler-oriented Architecture Research Demonstration Board) project, 1993.
  12. Principal Recipient: Advanced Micro Devices (AMD), 29K series evaluation boards and processors donation (~$10K) in support of the CARDBoard (Compiler-oriented Architecture Research Demonstration Board) project, 1993.
  13. Principal Investigator: extension of "Compiler-Oriented Architecture," Office of Naval Research (ONR) grant number N00014-91-J-4013 ($25). September 1, 1991 - August 31, 1994.
  14. Principal Investigator: extension of "Compiler-Oriented Architecture," Office of Naval Research (ONR) grant number N00014-91-J-4013 (~$100K). January 1, 1995 - December 31, 1995.
  15. Principal Recipient: Texas Instruments (TI), FPGA parts donation (~$70K) in support of the PAPERS (Purdue's Adapter for Parallel Execution and Rapid Synchronization) project, 1995.
  16. Principal Investigator: "Fine-Grain Cluster Technology," Intel (~$20K worth of PC hardware).
  17. Co-Principal Investigator (with E. J. Coyle and L. H. Jamieson): "Engineering Assistance for Community Service Organizations," U.S. Department of Education Fund for the Improvement of Postsecondary Education: Innovative Projects in Community Service (FIPSE), Award No. P116F50129 (~$71K), August 1, 1995 - July 31, 1997.
  18. Co-Recipient (with E. J. Coyle and L. H. Jamieson): Comdisco, Inc., equipment donation ($100K) to the Engineering Projects in Community Service (EPICS) program, October 1995.
  19. Co-Principal Investigator (with E. J. Coyle, L. H. Jamieson, J. L. Gray, K. T. Kornegay, and C.-M. Ong): "Hardware Prototyping Capability for a Community Service Projects Course in Electrical and Computer Engineering," NSF Instrumentation and Laboratory Improvement Program, Award No. DUE 96-50771 (~$160K), May 13, 1996 - May 12, 1998.

Hobbies

Outdoorsy Stuff
Fishing, canoeing, sailing, and bicycling (if my tires don't go flat again).
Driving Stuff
These are my '87 Golf and '97 Passat VR6. I guess I like VWs?

Here is the real reason that I bought the Passat. :-)
Indoorsy Stuff
MST3K (aka ) and other such things on my wall (gotta love those LCD projectors), Scrabble, Jenga, woodworking, photography, wines and cooking (although cleaning up afterward isn't much fun), and a few computer games.
Wierd Stuff
That's the SillyHack IV "Portable Array of Cheap Calculators" and its "SIMD adapter." I built this parallel computer as a gag gift for the roasting of Tse Feng at the 20th International Conference on Parallel Processing. The "SIMD adapter" is used to simultaneously press the same key on all four calculators....
Another example is building things like the 16-foot rig I use to drop a simulated ear of corn in sync with the ball in New York for my New Year's Eve party... for no apparent reason.

I have a brother!

My dad has a company!

HGD

This page was last modified May 01, 1998. [an error occurred while processing this directive]