Publications
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, and T. N. Vijaykumar
IEEE International Symposium on High Performance Computer Architecture (HPCA),
February 2002.
Evaluating Opportunity and Effectiveness of Cache Resizing to Reduce Energy Dissipation
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar
CACLM Technical Report #2001-001, Carnegie Mellon University,
June 2001.
Reducing Set-Associative Cache Energy via Selective Direct-Mapping and
Way-Prediction
Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, and Kaushik Roy
International Symposium on Microarchitecture (MICRO),
December 2001,
postscript,
PDF.
An Integrated Circuit/Architecture Approach to Reducing Leakage in
Deep-Submicron High-Performance I-Caches
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, and
T. N. Vijaykumar
IEEE International Symposium on High Performance Computer Architecture
(HPCA), 2001,
postscript,
PDF.
An Energy-Efficient High-Performance Deep-Submicron Instruction
Cache
Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, and
T. N. Vijaykumar
IEEE Transactions on VLSI, special issue on Low-Power Electronics and
Design, February, 2001,
postscript,
PDF.
Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron
Cache Memories
Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar
ACM/IEEE International Symposium on Low Power Electronics and Design
(ISLPED), 2000,
postscript,
PDF.
Dynamically Resizable Instruction Cache: An Energy-Efficient and
High-Performance Deep-Submicron Instruction Cache
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar
Technical Report 007, School of Electrical and Computer Engineering,
Purdue University, May 2000.
Design and Optimization of Low Volatage High Performance Dual
Threshold CMOS Circuits
L. Wei, Z. Chen, M. C. Johnson, K. Roy, and
V. De.
ACM/IEEE Design Automation Conference (DAC), 1998.
Double Gate Dynamic Threshold Volatage (DGDT) SOI MOSFETS for
Low Power High Performance Designs
L. Wei, Z. Chen, and K. Roy
ACM/IEEE Design Automation Conference (DAC), 1998.
