Resume
Statements
Research
Statements
Teaching
Statements
Schedule
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| Postal
Address: |
Mail Box #291, Purdue
University
1285 Electrical Engineering Building
West Lafayette, Indiana 47907-1285
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| Office: |
Room 286 MSEE
Building
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| Phone:
| 765.414.5136 Cell
765.494.0759 Office
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| E-Mail: |
kang18@purdue.edu
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| Education:
| B.S., Seoul National University,
Korea, 2002
M.S., Rensselaer Polytechnic Institute,
Troy, NY, 2003
Ph. D., Purdue University, West
Lafayette, IN, 2007 (expected)
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| Background &
Interests:
For the past decades, digital electronic industry has
shown phenomenal growth due to scaling of CMOS devices
over different technology generations. Scaling of
transistor dimension has provided higher computation
capability with increased energy efficiency and reduced
silicon area. However, as CMOS scaling goes below
sub-100nm region, a plethora of new design challenges
are emerging as a barrier for further scaling of
transistor dimensions. Some of these challenges include
ever-increasing variations in process parameters,
degradation in circuit reliability and fault/failure
tolerance, and increased level of leakage current. My
graduate research is focused on developing efficient
VLSI circuit design methodology considering such scaling
issues in nano-scale technology. I particularly focused
on emerging reliability issues in nano-scale CMOS
technology such as process parameter variations and
negative bias temperature instability (NBTI). The key
achievement of my work was analysis and modeling of
nano-scale reliability issues, development of efficient
circuit/system level CAD tools and circuit design
techniques to relax and minimize reliability degradation
in high performance ICs. Through number of different
projects, I and my research colleagues have launched
various design methodologies and tools which accurately
addressed one or more critical reliability issues, and
further, enabled automated circuit design flow.
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