Project Goals

The Multiplex Project proposes a novel architecture for future billion-transistor chips. Brute-force approach of just scaling current architectures to larger hardware structures to use the extra transistors will deteriorate the clock cycle time. Our approach to use the extra transistors is to employ a distributed on-chip architecture so that the harware structures themselves are not enlarged, but multiple copies of the structures are used to exploit the extra transistors. The key idea is that the distributed architecture unifies a uniprocessor and a multiprocessor by providing support for both sequential and parallel programs in the memory hierarchy. While sequential programs benefit from implicit (not specified in the program) parallelism via memory dependence speculation, parallel programs employ explicit (specified in the program) parallelism. Multiplex employs a memory hierarchy that will handle both speculatively and explicitly independent memory accesses in a unified manner.

Developing compiler support for the architecture is just as important. Speculative multiprocessing architectures extract parallelism implicit in programs that may be difficult or impossible to parallelize explicitly at compile time. By speculatively executing several tasks in parallel and detecting dependence violations, correctness is ensured while providing speedup. Optimally partitioning programs into these tasks is key to achieving good performance. The compiler support project focuses on applying all available information, including source-level profiling, run-time dependence information, and knowledge of performance tradeoffs, to develop effective methods for automated task selection.