Research Contributions

Professor Vijaykumar's research addresses some of the most important challenges in the field of high-performance microprocessor architecture. The challenges include transient faults, inductive noise, power dissipation, and wire delay, all of which are worsening due to CMOS scaling.

As the supply voltage is scaled down to reduce per-transistor power, transistors become more susceptible to transient faults due to particle strikes caused by radiation from packaging materials and cosmic rays. Vijaykumar's work (SRTR and CRTR) is the first to propose hardware-based recovery from transient faults. Supply-voltage scaling also causes the absolute noise margin to shrink. At the same time, current spikes due to variation in processor activity causes the inductive elements in the power supply to induce noise in the supply voltage exceeding the noise margin. Vijaykumar's work (pipeline damping and resonance tuning) has pioneered concepts in controlling inductive noise at the architecture level by limiting the variability in processor activity. Furthermore, supply-voltage scaling forces the threshold voltage of the transistor to be lowered in order to maintain high performance. However, lower threshold voltage implies exponentially more leakage current. Vijaykumar and his colleagues published the first technique (gated-Vdd) to reduce leakage in caches.

With his colleague, he has shown (SC++ paper) that sequential consistency can be made to perform as well as release consistency by employing some modest amount of buffering. This paper shows one way to settle a decade-long debate on memory consistency models in the architecture community, and has been included in the Readings in Computer Architecture.

Because wires do not scale as well as transistors, wire delay has become the leading hinderance to scaling of performance. Vijaykumar's graduate work (Multiscalar architecture) is the first distributed microarchitecture and introduced the concept of speculative threads. He proposed the first cache versioning protocol (Speculative versioning cache - SVC) to allow distributed caches to run speculative threads. Projects from Stanford (Hydra), Illinois (IA-COMA TLS), and CMU (Stampede) have built on Multiscalar and SVC. With his colleagues in grad school, he also proposed dynamic synchronization for memory dependencies.