Addressing hard errors (or defects), my PhD student Ethan Schuchman
and I propose a novel defect-tolerant and
testable microarchitecture.
In our work on wire delays, my PhD student Zeshan Chishti and I have argued
that SMTs do not have a wire-delay problem . To manage wire delays in large
caches, Chishti, Powell and I propose
NuRAPID . Recently, we have proposed
a new CMP cache to alleviate wire delays in CMPs.
In the soft-error project, Prof. Irith Pomeranz, my PhD students
Mohamed Gomaa and Chad Scarbrough and I propose using SMT and CMP to
provide recovery for SMT and
CMP without much
performance loss beyond detection. Recently, Gomaa and I have developed techniques
to trade-off coverage for performance.
In the low power project, Profs. Kaushik Roy and Babak Falsafi, my PhD
student Michael Powell, and I did one of the earliest work on leakage power
reduction in caches (which are the biggest problem for leakage)--
gated-vdd ,
DRI cache .
Addressing power-related issues,
Powell and I have proposed schemes
damping and tuning to reduce
inductive noise . In a recent paper, Powell, Gomaa and I propose
exploiting CMPs and SMTs to alleviate
power density.
In the speculative multithreading project, Prof. Rudi Eigenmann, his
PhD student Troy Johnson, and I proposed
a min-cut based technique to partition sequential programs into speculative
threads.
In the networking hardware project, my PhD student Jahangir
Hasan, my colleague Satish Chandra, and I proposed techniques for
efficient use
of DRAM bandwidth to improve network processor packet throughput . More
recently, Hasan and I proposed an IP Lookup scheme that scales well in all
the five factors of total memory, throughput, power, update cost, and
chip area.