Welcome to the Purdue VLSI Microarchitecture web page in the School of Electrical and Computer Engineering, Purdue University. In this project, we focus on techniques to improve the performance of general-purpose, high-performance microprocessors. Current projects include:

Microarchitecture to exploit Control Independence

Branch prediction employed by modern microprocessors incur mispredictions for the branches which are inherently hard to predict. The key idea is to skip over such "unpredictable" branches by continuing execution at the reconvergent point (where the taken and not-taken paths of the branch meet) in the control flow of the program.

Indirect-associative Caches: High Associativity at Direct-Mapped Speed

High set-associative caches have lower miss rates but longer access times but direct-mapped have higher miss rates but faster access times. We are investigating a design which is basically a high set-associative cache but embeds a direct-mapped access path. Accesses which hit in the direct mapped locations have fast access times, while accesses which hit in the set-associative locations have slower access times.

Reducing the Penalty of Conflicts in Branch Prediction tables

Modern microprocessors use hardware tables to learn the patterns of past branch outcomes (taken or not-taken) to predict future branch outcomes. Branch prediction tables are usually small due to access time constraints, causing many mispredictions due to conflicts in the tables. The key idea is to put replaced branch prediction entries into the L2 cache, merging program data (original instructions and data) with program meta-data (branch prediction entries) in the large memory hierarchy.