Research Summary

Sponsors: MARCO, SRC, NSF, Intel, IBM, DARPA, HP, Rockwell, ATT/Lucent

High Performance and Low Power Circuit Design

Low Voltage Low Transistor Threshold CMOS circuits with leakage control techniques. Such techniques include transistor stacking, multiple transistor threshold, and dynamic control of transistor threshold voltage.
Sub-threshold digital CMOS circuits for ultra low power operations where performance is of secondary concern (examples include medical applications such as hearing aids). Special circuit techniques are used for robust design.
Skewed CMOS logic: A static noise-immune logic family for high performance. Circuits show much better scalability than Domino logic with performance similar to that of Domino.
ICALP (Integrated Circuits/Architecture for Low-Power): Designed a dynamically re-configurable instruction and data caches (DRIi and DRId caches) for low power and high performance using a novel gated-Vdd circuit technology.
SOI (Silicon-On-Insulator) circuit design to effectively handle floating body effects in partially depleted SOI.
Array based performance predictable circuit architecture for the deep sub-micron regime.

Low complexity design of adaptive and non-adaptive digital filters using novel techniques such as differential coefficients, minimally redundant coefficients representation, factorization, etc. These techniques help us design multiplier-less filters.
Novel high-speed multiplier architectures suitable for vector scaling operations. Results show that our shared multiplier architecture when used in a 11 tap low pass digital filter is 40% faster than an implementation with fast Wallace tree multipliers.
Low complexity image compression using distributed multiplication.
Multimedia wireless communication for low power – channel coding, source coding, and modulation.

Dynamic noise modeling for high performance monotonic circuits.
Ldi/dt noise analysis and design of power and ground lines, effective placement of decoupling capacitors.
Analysis and optimization of inductive coupling

Developed techniques and methodologies for average power estimation of static CMOS and Domino logic at different levels of design abstraction – RTL, circuits, and behavioral level.
Logic and high level synthesis for low power based on above estimation technique
Maximum current estimation in CMOS circuits using a novel ATPG (Automatic Test Pattern Generation) based technique.

Designed both logic modules and routing architecture of anti-fused based FPGA’s at Texas Instruments, where I worked as a member of Technical Staff from 1990-1993. We published several papers on both logic module and routing architecture.
Developed CAD tools for anti-fuse based FPGA routing architecture synthesis.